This invention relates to compressing, decompressing and transforming a signal to a frequency domain representation wherein the frequency domain resolution can be improved as a result of compression.
The transformation of a signal to the frequency domain has numerous applications in signal processing, including spectrum analysis, detection and parameter measurement. The accuracy of these techniques depends on the frequency resolution of the frequency domain representation and the signal to noise ratio (SNR). Frequency resolution is inversely proportional to the number of samples of the signal, or the observation interval, used in the calculation of the frequency domain representation of the signal. In signal detection, resolution is important for resolving adjacent narrow peaks in a frequency domain representation. For signal parameter measurement, improved frequency domain resolution increases the accuracy of the parameter estimate, such as the center frequency of a signal. Many types of transformations are known in the art for converting a temporal or spatial domain representation to a frequency or spatial frequency domain representation. For digital or discrete signals these include the discrete Fourier transform (DFT), fast Fourier transform (FFT), discrete cosine transform (DCT), discrete sine transform (DST) and the z-transform. The frequency domain resolution fres corresponds to discrete frequency domain bin width fbin and depends on the sample rate fs and the number of samples N used to calculate the frequency domain representation by the following relation,fres=fbin=fs/N For the frequency domain resolution smaller is better because it leads to more accurate measurements. However, improving frequency resolution requires a larger number of samples N. This requirement can conflict with system limitations as described below.
Examples in the following discussion will use the FFT for the transformation from the time to frequency domain, but this is not intended to limit the scope of the invention to any particular transformation. Also, in this discussion, “real time” means a rate that is at least as fast as the sample rate of the digital signal. When analog to digital conversion is applied to an analog signal to form the digital signal, the sample rate is the rate at which analog to digital converter (ADC) forms the samples of the digital signal. When digital to analog conversion is applied to a digital signal, the sample rate is the rate at which digital-to-analog converter (DAC) forms the analog signal from the samples of the digital signal is the sample rate. The bit rate of a sampled, or digital, signal is equal to the number of bits per sample multiplied by the sample rate.
Many applications include converting an analog signal to a digital signal followed by a transformation of the digital signal to the frequency domain. When the ADC operates at high speeds, the frequency transformation processor is often too slow to process the flow of samples in real time, creating a bottleneck so that the samples must be stored until they are processed. Another bottleneck can occur when a data transfer interface, such as a bus, cable or network, cannot transfer the samples to the frequency transformation processor fast enough. For example, when the entire data transfer interface is used for transfer of the signal samples, the maximum data transfer bandwidth may be insufficient. Alternatively, when only a portion of the data transfer interface is allocated for transferring the signal samples, such as for example, by time interleaving the sample signals with other time critical data or with multiple streams of sample signals, the allotted bandwidth may be insufficient. In these cases, a capture memory stores the samples until they can be transferred and processed. Other bottlenecks can arise from the capture memory itself. The capacity of the entire memory or the portion of memory allocated for signal samples limits the number of samples received from the ADC that are available to the frequency domain processor. The speed at which the capture memory can receive the signal samples output from the ADC can also create a bottleneck. For example, a capture memory comprising static RAM (SRAM) with access time of 10 nanoseconds, can receive signal samples from an ADC at a sample rate of 100 MHz or less. An application requiring a higher sample rate from a higher speed ADC would require more a expensive memory architecture in order to receive samples at the higher rate. The memory access speed thus limits the real time processing bandwidth achievable by the frequency domain processor.
Compressing the signal can mitigate these limitations by increasing the number of samples in compressed form that can be stored in memory, increasing the rate at which they can be received by memory and increasing the rate of transfer across an data transfer interface. The increased number of samples available for the FFT improves the frequency resolution of the frequency domain representation. The frequency domain resolution is a significant factor for detection. Insufficient frequency domain resolution can cause the detector to fail, as will be demonstrated by an example in the Detailed Description section. Alternatively, when the frequency domain representation has a fixed resolution requirement met by an N-length FFT, compression reduces the storage and/or data transfer requirements for the N samples in compressed form. The capacity of the entire memory or the portion of memory allocated for signal samples can be decreased, thus reducing memory requirements or freeing existing memory for other purposes in the application. The speed required to receive the compressed signal samples by a capture memory is reduced, allowing the use of lower speed memory architectures. The bandwidth needed to transfer the N samples across a data transfer interface is also decreased, so the bandwidth capacity of the data transfer interface or the portion allocated for transfer of signal samples can be reduced. Compression allows more efficient use of memory and data transfer resources, thus lowering the cost of the system.
In the commonly owned U.S. Pat. No. 7,009,533 B1 (the '533 patent), entitled “Adaptive Compression and Decompression of Bandlimited Signals”, dated Mar. 7, 2006 and incorporated herein by reference, the present inventor describes algorithms for compression and decompression of certain bandlimited signals. In the commonly owned and copending US Patent Application, application Ser. No. 11/458,771 (the '771 application) entitled, “Enhanced Time-Interleaved A/D Conversion Using Compression,” filed on Jul. 20, 2006 and incorporated herein by reference, the present inventor describes compression of a bandlimited signal that is sampled by a parallel time-interleaved analog to digital converter (TIADC). The compression methods described therein are designed to take advantage of the parallel architecture of the TIADC. In the commonly owned and copending US Patent Application, application Ser. No. 11/553,147 (the '147 application), entitled “Data Compression for a Waveform Data Analyzer”, filed on Oct. 26, 2006 and incorporated herein by reference, the present inventor describes compression and decompression of a signal having recurring waveform states and teaches algorithms for this particular type of signal.